As a fabrication process technics has been enhanced, the degree of integration of a semiconductor memory device in particular a dynamic random access memory DRAM device has been increased. As such a result, a size of each memory cell thereof and a space (or "pitch") between each bit line pair thereof have been reduced. As well-known, the DRAM device uses a folded bit line scheme and a shared sense amplifier scheme to lay out the sense amplifier within a reduced pitch. This is disclosed in U.S. Pat. No. 5,774,408, entitled "DRAM ARCHITECTURE WITH COMBINED SENSE AMPLIFIER PITCH". The DRAM device comprises bit line isolation transistors, bit line equalization transistors, p-latch sense amplifier, selecting transistors, and n-latch sense amplifier, which are corresponding to a bit line pair consisting of true and complementary bit lines (e.g., BL and BLB).
FIG. 1 shows a prior art layout arrangement of transistors (also, column selecting transistors) for selecting a bit line pair so as to be connected to corresponding data line pair (not shown). In FIG. 1, a reference symbol Y indicates a pitch within which four bit line pairs (i.e., eight bit lines) are laid out, a reference symbol S indicates a space between active areas 1 in which the selecting transistors are formed respectively, and a reference symbol L indicates a length (in which a selecting transistor having a source, a drain and a channel is formed) of each active area 1. Wherein the length L can be determined by a gate length, bit line to source contact area, drain to data line contact area, a space between the gate and the contact areas, and spaces between the contact areas and the drain and between the contact areas and the source. According to the prior art of FIG. 1, it can be seen that the selecting transistors corresponding to a bit line pair (or two bit line pairs) are laid out within a pitch Y of (2L+2S) in which eight bit lines, that is, four bit line pairs, are laid out.
The arrangement of the selecting transistors connected to bit lines is restricted by the space between bit lines of any one of bit line pairs. If the degree of integration is increased more and more, the space therebetween is also reduced, making it impossible that the selecting transistors are laid out within the space or pitch (2L+2S).
Referring to FIG. 2 according to another prior art, a layout arrangement of transistors for selecting bit line pair so as to be connected to corresponding data line pair is to lay out the selecting transistors within a pitch Y' less than 2L. In this case, the selecting transistors are laid out within the pitch Y' of (3/2L(L+L/2)+2S+.alpha. wherein, L&gt;(L/2+.alpha.)&gt;L/2) less than (2L+2S) of FIG. 1.
The higher the degree of integration of the DRAM device, the less a size of each memory cell therein and a space between bit lines. In this case, it is impossible that the selecting transistors are laid out the pitch Y', that is, (3/2L+2S+.alpha.). Therefore, it is needed to ensure the selecting transistor area so as to be laid out within a pitch less than (3/2L+2S+.alpha.).